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发表于 2017-10-15 16:31:44
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查了一下cpu,难道是四核的？
) M0 K1 ^1 o2 q- l- l* k0 B8 k~ # cat /proc/cpuinfo7 V% ?- C+ j! }% K4 u2 f9 t
system type : EcoNet EN751221 SOC
# O+ T2 K0 _5 r3 q x6 f' Wprocessor : 0" y# x0 K5 g4 u0 I/ K4 v
cpu model : MIPS 34Kc V5.8! ?8 U; K" |6 t# v* z2 K
BogoMIPS : 598.015 t2 P7 V/ P- R) s. l
wait instruction : yes
$ @& w, C! l, h* `! S/ p6 u2 g3 vmicrosecond timers : yes
5 N1 e* x- z" O/ E$ Etlb_entries : 648 @9 M! }7 Y) S [2 ~* y5 l. q/ w
extra interrupt vector : yes
5 ~( `* U! [* z- t: Ihardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
* B2 X- Q/ @( F" y3 R1 H' \& ^- HASEs implemented : mips16 dsp mt/ I( P* e M. P! {5 q9 R
shadow register sets : 1
, s h+ ]% ?2 m L; w6 Ocore : 0/ s3 W6 z. _2 `& U% K
VCED exceptions : not available
" z6 Y! |4 f6 {VCEI exceptions : not available
3 r1 x: k5 u# z r) c( C l' B' T) ]
processor : 1
# s5 R& O) Q3 k" icpu model : (null) V5.8
$ E. X$ n4 s1 mBogoMIPS : 448.92& h7 n. `; o+ h% c* b2 N
wait instruction : yes+ n+ \6 b- U: H) k5 w! s6 Y% x& W
microsecond timers : yes8 y" V8 w$ q$ p
tlb_entries : 64
2 L2 I& J) ^- K7 Z5 mextra interrupt vector : yes7 H* p. t* y# W3 f% P: u5 n
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
2 L+ Z' l8 \ u2 p2 GASEs implemented : mips16 dsp mt
5 e9 {1 f9 y1 q; w, {shadow register sets : 1
# s: K5 f. @. f: Q8 s5 c3 ycore : 0
$ [8 p, z% G; W! v& y8 d4 mVCED exceptions : not available
. v$ V% k U- SVCEI exceptions : not available
4 G) k5 \6 L0 y. w) Q+ U$ u" x8 I" }: k, K
processor : 2
R/ B8 [/ J/ U. C8 ~4 pcpu model : (null) V5.8
& b5 `9 g- I. ]' g N! lBogoMIPS : 448.92
* J g Q, x8 _; {+ Kwait instruction : yes/ q V, V: D3 Q8 l
microsecond timers : yes
- `8 w* u% }( i8 \( t5 ^* Ptlb_entries : 64
2 I0 A. X$ Y) H% k3 I1 xextra interrupt vector : yes
: q3 E w9 r' V/ \7 c" _hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
( X$ F3 `; j2 {# _1 U# n9 lASEs implemented : mips16 dsp mt' q9 N W9 I- b9 f+ _1 S
shadow register sets : 1
2 ?( I7 p/ X& k/ m0 a# mcore : 0
8 J+ A' s: V1 j0 MVCED exceptions : not available, R2 U4 _8 G, I: g5 d
VCEI exceptions : not available' U2 W5 N3 M0 s }
* ]7 a! V/ ^# I0 E* [. |
processor : 31 N* I' Q! i6 ^7 L* Z3 }
cpu model : (null) V5.8
6 ?/ o; f! v0 BBogoMIPS : 448.92
8 l2 B9 L; v1 \7 Z$ g4 iwait instruction : yes
* F6 A6 A& F5 t, lmicrosecond timers : yes3 H1 J: b8 {0 L& S6 O
tlb_entries : 646 w5 X4 U/ p2 Z& ^2 l+ p, x
extra interrupt vector : yes; N2 P/ E2 A& k I9 I! ~2 l0 Z
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
r0 `6 n! p4 N( ]2 L4 S* YASEs implemented : mips16 dsp mt
$ _6 F+ I* W) tshadow register sets : 1 D& T: l: Z! t2 Y- J1 Z
core : 0
! n" L+ }1 L- I3 n+ R- YVCED exceptions : not available
* s2 v% J- v7 d1 {( ?. \1 TVCEI exceptions : not available
/ o+ W; @4 J+ j. R! ~7 d; T* a6 }( e" k, n2 p+ f P
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