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发表于 2017-10-15 16:31:44
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查了一下cpu,难道是四核的？. X& r* Y8 r" C" I% P) s% P
~ # cat /proc/cpuinfo0 D) g! g) u, _1 m, E- k$ |1 |
system type : EcoNet EN751221 SOC' Q3 @5 A8 [% y% A0 w, h+ t
processor : 0$ @; r+ I) b: e5 w! B" v3 {% G
cpu model : MIPS 34Kc V5.81 i5 E. D6 c- L( U2 p5 x$ [& c
BogoMIPS : 598.012 C8 W8 P) T; Q7 G5 g. _
wait instruction : yes
. ]$ i3 ~! {8 c* o. K- Smicrosecond timers : yes
3 e+ k- K* v- D8 Jtlb_entries : 64" S9 ^% S" X D6 P. u
extra interrupt vector : yes$ ~4 p! P5 i) u+ D- o' L
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]. K p7 v8 E8 ^$ w7 a- A
ASEs implemented : mips16 dsp mt
+ N# I4 C; d3 _& X( Z7 z4 Ashadow register sets : 1* q+ l- D9 z% d' ^# ^, L, m
core : 02 ?# S: K" ^3 E i: d6 n9 G0 }
VCED exceptions : not available/ j- C o0 g% j5 U2 O# \
VCEI exceptions : not available
. u2 y" ^7 V, q, @$ }
* I9 |- T B; ^- C$ uprocessor : 18 d2 f+ X1 l1 K& H
cpu model : (null) V5.8
# g; q! z( R; @( n$ R: p# K; UBogoMIPS : 448.92) O$ h. P$ P( `4 p% x* A$ r
wait instruction : yes0 Y* H6 E6 Y0 k
microsecond timers : yes3 }( v( X; S$ E7 j
tlb_entries : 64% u6 ?2 P# x# b) H- X
extra interrupt vector : yes% {( {& k* t$ t
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
0 n) k0 n: r7 s1 Q, D4 z7 rASEs implemented : mips16 dsp mt
$ ] o+ V! D+ o' S6 zshadow register sets : 1 k9 y& c4 I# ^5 {) s
core : 08 l Y C3 W/ y4 m" k
VCED exceptions : not available
2 N2 A/ f7 ^3 h ?% \+ ^9 kVCEI exceptions : not available X! _7 w; R: j. B
: W5 P" @- Y+ e/ x( b6 H5 I' {
processor : 2
, K* L9 C: F! P0 D$ Jcpu model : (null) V5.8
& Z C/ Y5 w" }6 r+ H& r/ rBogoMIPS : 448.92
& d v$ K6 p! V; {wait instruction : yes
* S$ f. V( y: Q; H+ F2 Rmicrosecond timers : yes
; {% G- C" p( n, M( btlb_entries : 64
& ?5 b, @1 `1 p2 }! t7 n# T2 K sextra interrupt vector : yes
0 F; J9 W- h0 y" d! P! @. P9 s' m; ~hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
. Z0 Y9 ?: q. LASEs implemented : mips16 dsp mt
) i* V/ C, t. Eshadow register sets : 19 G, H( U5 O* o5 k
core : 0& I2 B; t0 R, W: F1 |- U& [
VCED exceptions : not available
1 _8 i- @1 b7 C5 L( W$ wVCEI exceptions : not available
& E& B% b7 E5 a5 Q& Y# l$ ]
7 K5 B, r0 q! q+ o8 l. o5 }# h0 Yprocessor : 39 k& L( A+ o! G. c! G2 b9 K9 W
cpu model : (null) V5.8
8 X9 j& N9 A0 X% f: yBogoMIPS : 448.92
8 R3 `: v! _ Q7 u/ qwait instruction : yes2 l/ h8 N; r; s4 m# O" \% g
microsecond timers : yes0 c e: S: p+ R; R
tlb_entries : 64
$ k* {+ d) W. ~ f2 x, z1 k8 Q" `extra interrupt vector : yes
1 j5 ^5 L* R7 v' y3 uhardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]1 o9 j- ^# r. L+ `" i$ M
ASEs implemented : mips16 dsp mt
0 f* |% C$ p# {shadow register sets : 1! \* T% G) @6 I/ ]
core : 0
: J" s+ C& v9 j& }2 c8 |VCED exceptions : not available
! v& ~* D+ x+ r2 c* M/ Y* f+ H7 FVCEI exceptions : not available
0 f' n7 E G B/ U. w2 V6 [) ?$ Q
0 w! }- H" _6 s! J. Q7 G) \' ?- z~ # |
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