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发表于 2017-10-15 16:31:44
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查了一下cpu,难道是四核的?! B* t% A, c, ` I
~ # cat /proc/cpuinfo
' j: K/ w. A- g1 ~8 ~$ W! s0 xsystem type : EcoNet EN751221 SOC
* N" Q6 x- G% Y" U* Gprocessor : 01 L" W" P$ X0 Y+ P
cpu model : MIPS 34Kc V5.8
! } c' ^( l% Q2 Z% j0 }8 b9 Q2 I- fBogoMIPS : 598.01
, a- i) n7 v5 N. M o! wwait instruction : yes
8 p% \) }% J- v+ Pmicrosecond timers : yes
( L" {$ N1 e j& @' m0 r4 Ntlb_entries : 646 g0 \1 B) L; o. `- Q
extra interrupt vector : yes; E9 _/ F" s, \& Y3 z2 ]
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]% U% ]& c# z5 ^
ASEs implemented : mips16 dsp mt
. o* u5 {7 M- j2 F& d( m0 O* Tshadow register sets : 1: e8 y/ N/ l4 Z$ u4 @; T6 }
core : 0
) I6 Z/ J$ U5 `% K5 W; s$ dVCED exceptions : not available% S8 U0 M z! n2 f. a& w7 {3 c
VCEI exceptions : not available
/ ^& V$ g e: T8 V- k- u" [( e& t4 z8 J; }8 @! j
processor : 1
0 D* p+ W/ Z* v0 \+ m% L2 Ecpu model : (null) V5.89 N) P' `5 B2 V! E7 X
BogoMIPS : 448.924 e7 U+ o2 `9 S! x1 I) N( ?( T( _
wait instruction : yes b; G/ R1 y8 {8 j* |* @" q
microsecond timers : yes
. H H$ i& s6 Z6 C7 etlb_entries : 64% V7 X4 d d4 c
extra interrupt vector : yes; p9 v" I/ L3 g/ ~
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]6 T2 [+ r5 L( F2 Y
ASEs implemented : mips16 dsp mt9 |( K9 }2 x8 @8 e: e8 {
shadow register sets : 13 G+ D" _/ n$ S2 z8 i. W1 D, x
core : 0" H1 C; y0 C# e
VCED exceptions : not available0 Z( B- N) w1 K- P; U. j9 b
VCEI exceptions : not available4 Y/ k) ` @. T$ K, A, W- O9 ^
% L6 p5 i; a2 p6 ~) G: U( ?8 }8 n
processor : 2) P8 H/ `% S4 \2 J
cpu model : (null) V5.8: [) v5 }3 G" u( Y: f! H J6 N7 T
BogoMIPS : 448.92: n: n* n, I) D5 C* V
wait instruction : yes, s. w: a" I- A( q0 \; _
microsecond timers : yes
/ N3 J2 Z, d q$ P0 ctlb_entries : 64/ E" a8 R3 F0 N3 ?/ U4 O5 ~
extra interrupt vector : yes
: c, o& Q% g' t8 q- l! A6 Jhardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]
1 ^6 f; d+ g: w* z3 zASEs implemented : mips16 dsp mt4 u$ i$ t8 z( _8 s: J% x
shadow register sets : 1
, p0 p7 d0 y5 @core : 0
0 u& |, ~" v# G; ?4 d3 ^$ |2 k! n. `VCED exceptions : not available+ w3 w7 H* r+ A" b
VCEI exceptions : not available4 U- J+ o5 e# S; }+ x0 @ |& J( Z
+ s" E d# u/ R) m' r; Y& E) |processor : 3+ B9 ~4 _) l N3 M
cpu model : (null) V5.8: Y, A5 @- W( g* v+ K
BogoMIPS : 448.92/ G+ A- [' O$ h2 x
wait instruction : yes. L' G8 o3 q8 T0 s+ a2 L3 _
microsecond timers : yes0 a- ^" C) A A
tlb_entries : 64' R# h J6 T+ z7 \& C, W s% }
extra interrupt vector : yes2 W3 G3 \. { _" D% \( k- f( G
hardware watchpoint : yes, count: 4, address/irw mask: [0x0ff8, 0x0328, 0x0ffb, 0x02c8]7 q/ Q5 p, q$ B7 y1 J) H
ASEs implemented : mips16 dsp mt
2 m0 h, w3 U0 K# J- p9 f. oshadow register sets : 1: K, g& |) j$ ~* v7 a/ B
core : 0
, j l% H: s& eVCED exceptions : not available
; ? `+ K3 t% u \9 bVCEI exceptions : not available
% y* N! _ b l3 S, K
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