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按1-9都不行: K! M' r+ `, k5 L1 S! z3 o" x
[05000C07][05000C07]: i8 G8 G7 j& N- d3 R& ^, Z4 i
DDR Calibration DQS reg = 00008787
1 ?. C3 n3 F0 J6 k3 R( I' x) B+ Y. l2 n
# t9 D9 k# ^5 j' F
U-Boot 1.1.3 (Jul 25 2018 - 03:19:13)1 _7 a4 e; z& \6 D) W/ L6 a) P0 K
. X8 w: A& E h: v' N( C" \6 Q: P
Board: Ralink APSoC DRAM: 64 MB& v. e# D0 o2 R% z
Power on memory test. Memory size= 64 MB...OK! u! c; r, j4 [ X
relocate_code Pointer at: 83fa8000
- z3 A5 Q( s$ |RT2880_RSTSTAT_REG 0xc00300006 j" d% U' l4 `# Q
***************************
' V4 J! w$ u' `. {- m% t" ]Board power on Occurred. T+ f) ~9 e$ M/ r+ y% y
***************************2 m, z) B; M+ d: w$ h, v# Q
flash manufacture id: ef, device id 40 18" s3 @' b) B8 U' \( K* c, @
find flash: W25Q128BV6 W* y& ~' V @9 c
env is right!
0 A% S: }9 @$ Q3 Y" D" @7 D============================================
4 B! ]8 k) n. [. H' SRalink UBoot Version: 4.3.0.0
/ W2 |+ a/ h3 r& i7 H ~' O8 ]6 n--------------------------------------------
3 L3 a9 j1 S1 ]5 F1 r5 JASIC 7628_MP (Port5<->None)# M: r% e6 ?% s; h1 F1 {
DRAM component: 512 Mbits DDR, width 16
1 O- i* P& u* i7 b s4 D7 CDRAM bus: 16 bit* ?% F% h s) N2 H
Total memory: 64 MBytes. m2 L8 }! V* x/ X2 q4 C) v
Flash component: SPI Flash
' E3 {7 N( j( Z$ u9 _Date:Jul 25 2018 Time:03:19:13' N$ `( q$ O0 v! N9 L3 j
============================================- n" b# C- l2 m* \+ _( Z0 g
icache: sets:512, ways:4, linesz:32 ,total:65536
" P% A0 d6 F$ [' q! `9 bdcache: sets:256, ways:4, linesz:32 ,total:32768
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##### The CPU freq = 575 MHZ ####
# C8 ]2 C6 H- }: U+ K estimate memory size =64 Mbytes
- _& h8 O" `& `( N2 }RESET MT7628 PHY!!!!!!
! b8 ]4 x, [7 r6 S( ^; L: p6 GPlease choose the operation:
* c7 ?' f: h' m$ X0 w, z& I 1: Load system code to SDRAM via TFTP.
4 C# I5 N4 S; `$ T. ]; n 2: Load system code then write to Flash via TFTP.
2 v. s, {0 v, y2 \: w/ B 3: Boot system code via Flash (default).
0 ]: G+ D5 S$ N! P5 p 4: Entr boot command line interface.& G( r% Q. m5 I# g2 g1 i! \8 a0 c
5: Load common filesystem then write to Flash via TFTP.
- V3 Z n" {0 \. v6 h' Z* ] 7: Load system code via web.
) u5 R, ?* Q, R$ K: U 9: Load Boot Loader code then write to Flash via TFTP.
2 b$ H0 Y Y( w! l! R
; |. ?/ K$ k6 F* Q0 P3 m n3: System Boot system code via Flash.; ^2 r. M% U: x3 \- |
Booting System 1* n, Z( m' r/ p. O1 x0 i
Erasing SPI Flash...
7 P$ G" ], h$ K! B. Fraspi_erase: offs:30000 len:100009 l- V& w7 Z' J7 {
.
3 p* E0 e1 T6 Y+ m+ n2 W" [$ G, xWriting to SPI Flash...+ H/ e* z6 x/ S, s7 A3 ]& x
.
) b. M- s0 m; F" W- Q7 Y" E1 }% udone1 X1 g- q; j! H) m3 {2 |! G9 W* w: N
## Booting image at bc180000 ...2 w9 Z: I" r, h2 v4 \6 @1 }: C9 y
Image Name: MIPS OpenWrt Linux-3.10.14
! k% u+ B5 e" Z- h% G% u" Q5 E Image Type: MIPS Linux Kernel Image (lzma compressed): m3 z* w' Z6 E9 G
Data Size: 1425851 Bytes = 1.4 MB! r- K% V& s* T
Load Address: 80000000
# p; i, u& P5 \' c+ G) d Entry Point: 80000000$ ?) v2 q9 }, g
Verifying Checksum ... OK
, f/ I9 s$ q$ w Uncompressing Kernel Image ... OK+ L& J+ W9 N0 X7 U6 X9 \
commandline uart_en=0 factory_mode=0 mem=64m root=/dev/mtdblock9) h; @) c" I: h
No initrd' C% W0 G f& a: _ t
## Transferring control to Linux (at address 80000000) ...6 }) v. U8 v' [; O {) v* W. m2 T w
## Giving linux memsize in MB, 64
# P4 T" x- c0 ?7 b) v& ^
- t2 Q' W4 m2 @ a" ~Starting kernel ...* ?$ O4 C5 u% K2 m# P, ]1 i
: M; Y x! H( x. A% P+ {1 ^! L3 z3 S* H& U! `# q
LINUX started...
# Y. y& ?. g9 {4 `% T& c% A$ n7 `/ s4 @) n9 K
THIS IS ASIC# |: ~$ N; B. i
[ 0.000000] Initializing cgroup subsys cpuset
" U0 }! i7 r0 i4 j @1 V9 A+ C3 x2 E[ 0.000000] Initializing cgroup subsys cpu
+ v: r1 d% V- }" s# P: K. n[ 0.000000] Linux version 3.10.14 (jenkins@dea8cc7a4bde) (gcc version 4.6.3 20120201 (prerelease) (Linaro GCC 4.6-2012.02) ) #1 MiWiFi-R3A-2.18.40 Thu Nov 1 11:25:58 UTC 2018
% `$ p! k+ X8 ~# ^. Z( V/ Y5 _0 R+ W[ 0.000000]2 x" `6 }5 B, M. U2 J
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发表于 2019-11-30 19:14:19