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发表于 2015-10-25 00:00:08
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显示全部楼层
http://www.tp-link.com/en/download/TX-VG1530.html
CPU @ %dMhz, L2 @ %dMhz
No L2
DDR%s @ %dMhz, TClock @ %dMhz
Shutting down unused interfaces:
PON
SATA
Switch
3xFE-PHY
GE-PHY
SDIO
PCI-E 0/1
Crypto
XOR engine 0/1
USB 0: Device Mode
USB 0: Host Mode
Marvell monitor extension:
pcieTune freq Current mode is SatR=%d, CPU=%dMHz, DDR=%dMHz
freqval Current mode is 0x%x.
sscg Current SSCG mode is %d
tclk Current TCLK mode is %d
Current mode is SatR=%d, CPU=%d MHz, DDR=%d MHz, L2=%d MHz.
pon Current Pon mode is %d
pexclk Current PEX-0 Clock configuration is %d
Current PEX-1 Clock configuration is %d
l2exist Current L2 Exist mode is %d.
Usage: sar read [options] (see help)
SatR | cpuClk| ddrClk|
%3d | %5d | %5d |
SSCG Mode:
0 - SSCG enable
1 - SSCG bypass (disable)
TCLK Modes:
0 - 166 Mhz
1 - 200 Mhz
# cpuClk ddrClk l2Clk
%d %d %d %d
0 - 125 Mhz
1 - 166 Mhz
2 - 200 Mhz
3 - 250 Mhz
PEX Clock Configuration:
0 - PEX_CLK pins are input pins
1 - PEX_CLK pins are output pins
Select EPON or GPON operation mode:
0 - GPON Mode
1 - EPON Mode
Select L2-Exist mode:
0 - L2 is disabled.
1 - L2 is enabled.
Usage: sar list [options] (see help)
Write S@R failed!
Mode not supported!
Write S@R failed.
Usage: sar write [options] (see help)
SatR Sample At Reset sub-system
list freq - prints the S@R modes list
SatR list sscg - prints the SSCG modes list
SatR list pexclk - prints the PEX Clk modes list
SatR list tclk - prints the TClk modes list
SatR list pon - prints the Pon modes list
SatR list l2exist - prints L2-Exist modes list.
SatR read freq - read and print the CPU / DDR / L2 frequency
SatR read freqval - read and print the frequency value
SatR read sscg - read and print the SSCG value
SatR read pexclk - read and print the PEX Clk value
SatR read tclk - read and print the TCLK value
SatR read pon - read and print the Pon type
SatR read l2exist - read and print L2-Exist mode.
SatR write freq cpu ddr l2 - write the S@R with cpu, l2 and ddr values
cpu: new CPU clock (in MHz)
ddr: new DDR clock (in MHz(
l2: new L2 clock (in MHz)
SatR write freqval <frequency value> - Write new value for CPU / DDR / L2 frequency.
SatR write sscg <0/1> - write the SSCG value with 1 or 0
SatR write pexclk <unit 0/1> <0/1> - write the PEX Clk conf
SatR write tclk <0/1/2/3> - write the TCLK value
SatR write pon <0/1> - write the Pon type
SatR write l2exist <0/1> - Set L2-Exist mode.
target unknown %s %d:
win%d - %s base %08x, disable
PEX%d:
Pex Bars
Pex Decode Windows
default win - Expansion ROM - USB ETH XOR Sata %s%x Rev %d
MV88F 88F6510 Z2 88F6530 Z2 88F6550 Z2 88F6560 Z2 88F6510 A0 88F6530 A0 88F6550 A0 88F6560 A0 88F6601 A0 SDRAM_CS0 SDRAM_CS1 SDRAM_CS2 SDRAM_CS3 DEVICE_CS0 DEVICE_CS1 DEVICE_CS2 DEVICE_CS3 PEX0_MEM PEX0_IO PEX1_MEM PEX1_IO INTER_REGS NAND_NOR_CS SPI_CS0 SPI_CS1 SPI_CS2 SPI_CS3 SPI_CS4 SPI_CS5 SPI_CS6 SPI_CS7 SPI_B_CS0 BOOT_ROM_CS DEV_BOOTCS CRYPT1_ENG CRYPT2_ENG PNC_BM ETH_CTRL PON_CTRL NFC_CTRL AHB To MBUS Bridge:
CPU Interface
no such
%s (Rev %d) Marvell Feroceon ARM926 ARM946 ??? (0x%04x) (Rev %d) L2 Enabled L2 Disabled L2 ECC Enabled L2 ECC Disabled L2 Prefetch Disabled L2 Prefetch Enabled Write Allocate Enabled Write Allocate Disabled CPU Streaming Enabled CPU Streaming Disabled CPU Config Reg = 0x%08x
L2 Config Reg = 0x%08x
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